1. Field of the Invention
The present invention relates to an analog output buffer circuit, and particularly to an analog output buffer circuit for a flat panel display.
2. Description of Related Art
Because of being able to integrate a driving circuit and a control circuit to a display panel, low temperature poly-silicon (LTPS) process is widely used in LCD devices. However, comparing to single crystal silicon, a typical LTPS still has some problems to overcome, e.g., low carrier mobility, high cut-off voltage, uneven electrical property of thin film transistors (TFTs) and less stable process, all of which may cause difficulties of circuit integration and circuit design.
Moreover, according to an LTPS LCD panel, the impedance at the signal side is different from that of the panel side. Therefore, direct input of the signals from the signal side to the panel side is likely to cause a signal distortion and an incorrect gray scale in display. Accordingly, an analog output buffer circuit is usually employed between the signal side and the panel side for driving the load of the panel side. The output buffer circuit must display the entire signal inputted by the signal side, and at the same time isolates the signal side and the load of the panel side, thus avoiding the signal distortion of the signal side because of the load variation at the panel side.
Improperly designed output buffer circuits or uneven electrical property of poly-silicon TFTs cause the distortion of the signals outputted from the output buffer circuits. In other words, buffered signals which are different from the original signals transmitted from the signal side will lead to a poor display quality. Therefore, what is needed is to provide an analog output buffer circuit for driving an LTPS display, which can overcome the disadvantage of analog output buffer circuit without stable quality in LTPS manufacturing process.
Referring to FIG. 1, a conventional analog output buffer circuit for a display panel is illustrated. According to FIG. 1, the analog output buffer circuit includes a N-type poly-silicon transistor N10 and a P-type poly-silicon transistor P10 connected in series between a voltage source VDD and a voltage source VSS. An input node IN is electrically connected to a gate of the TFT N10 and a gate of the transistor P10. An output load capacitor CL is electrically connected between an output node OUT and the ground voltage GND. The output node OUT is also electrically connected to a common node of the transistor N10 and the transistor P10. Herein, the capacitance of the output load capacitor CL is the total capacitance of the pixels electrically connected to the output node OUT on the panel.
In operation, an input signal Vin is inputted from an input node IN, and an output signal Vout is outputted from the output node OUT. The input signal Vin and the output signal Vout are illustrated in FIG. 2. It can be known from FIG. 2 that when the input voltage rises from 0 V to 6 V, the output voltage apparently can not rise to 6 V. That means the output signal obtained from the output buffer circuit inputted by the input signal does not have a voltage level same as that of the input signal.
FIG. 3 illustrates another conventional analog output buffer circuit for a display. The major difference between the circuit shown as FIG. 3 and the circuit shown as FIG. 1 is that the circuit shown as FIG. 3 employs an input capacitor C30 and switches S31, S32 and S33 to eliminate the drawback of different voltage levels between the input and the output signals in the circuit shown as FIG. 1. Referring to FIG. 3, as the switches S31 and S33 being turned on, a voltage difference is stored in the input capacitor C30, then the switches S31 and S33 are turned off and the switch S32 is turned on, then the input signal Vin has a voltage difference added at the input capacitor C30, thus the original input signal level is promoted thereby.
However, the transistor N10 is not ideal as a switch, especially when it is turned off. In other words, even the output signal Vout has a promoted voltage level to have the transistor N10 turned off, a leaking current may still flow through and continue charging the output load capacitor CL and therefore make the voltage level of the output signal Vout higher than the voltage level of the input signal Vin. The input signal Vin and the output signal Vout of a circuit shown as FIG. 3 are illustrated in FIG. 4. It can be known from FIG. 3 that a voltage level of the output signal apparently rises with time up to a level over the voltage level of the input signal, which causes an output signal Vout distortion.